AI models can change much faster than custom chips can be designed and manufactured. As a result, chip companies may spend years developing hardware for AI workloads that have already changed by the time the chip is ready.
Architect Labs is testing whether AI can shorten the design process. In an August paper, the startup says two human architects gave its AI system a high-level specification, and the system produced Redwood, an AI inference accelerator running on Field Programmable Gate Array (FPGA) hardware, in less than two weeks.
The company then used an AI model running on Redwood to identify possible improvements for future versions of the accelerator.
Redwood shows how AI could reduce the time required to design specialized hardware. However, the current system runs on an FPGA, and Architect Labs has not yet manufactured a Redwood chip.
Two architects defined the requirements. AI completed much of the design work
According to the Redwood paper, two human architects started by describing what the accelerator needed to do. Architect Labs says its AI system then created the performance model and RTL, the code engineers use to describe how a digital circuit should operate.
The system also produced verification environments, firmware, drivers, and compute kernels. These are the components needed to test the design and run AI workloads on the hardware.
Architect Labs reports that every part of the design achieved more than 95% code and functional coverage through its own verification tools, commercial chip-design software, and hardware testing.
The company also says it could make specification changes, redesign the affected parts, verify the changes, and run the updated version on FPGA hardware in less than 48 hours.
This shorter development cycle could help chip teams respond more quickly to changes in AI models. Chip architectures are often decided years before the final hardware reaches customers, while AI workloads can change within a few months.
VentureBeat reports that Architect Labs wants to give hardware teams more flexibility to update designs as workload requirements change.
Redwood still has to prove its performance in manufactured silicon
Redwood Nano currently runs models such as Llama and Qwen on an FPGA. An FPGA is reprogrammable hardware that engineers often use to test chip designs before manufacturing a final version.
On the FPGA, Redwood Nano reached 12.1 tokens per second on Qwen3 0.6B. Nvidia's Jetson Orin Nano reached 28 tokens per second in the same comparison.
Architect Labs expects different results if Redwood is manufactured using Samsung's 8nm process. The company estimates that the chip would reach 49 tokens per second while using about half the power of the Jetson Orin Nano baseline.
Based on those estimates, Architect Labs projects a 3.4x improvement in performance per watt.
Those results are simulations rather than measurements from a manufactured Redwood chip. Actual performance could change once the design goes through physical chip development, manufacturing, and testing.
EE Times also describes Redwood as an FPGA implementation and presents the project mainly as evidence that Architect Labs can quickly move from an initial specification to a working prototype.
The next stage will test whether the same design process can produce similar results in manufactured hardware.
An AI model running on Redwood identified improvements
Architect Labs also tested whether an AI model running on Redwood could contribute to the next version of the hardware.
The researchers ran Qwen3 on Redwood and connected the model to the company's chip-design system. They then generated multiple responses from the model while looking for changes that could improve the accelerator.
According to the researchers, the process identified possible timing improvements and software kernel optimizations.
The sequence worked like this: AI helped design Redwood, Redwood ran an AI model, and the model then suggested changes that could improve future versions of the accelerator.
Architect Labs describes this process as an early example of "recursive self-improvement." The current experiment is more limited. Qwen3 proposed optimization ideas within a hardware development process managed by researchers.
Redwood has not shown that an AI system can independently redesign, manufacture, and deploy new generations of hardware.
The experiment does show how AI models could become part of the hardware development process. A chip-design system could test a workload, identify performance problems, and use those results to guide later design changes.
Recent Nvidia platforms show how much AI performance depends on specialized hardware and software. Architect Labs is testing whether AI can reduce the time required to design that hardware.
Redwood now has to move from FPGA testing to manufactured silicon. If Architect Labs can keep similar development speeds through chip manufacturing and validation, companies may be able to update specialized AI hardware more frequently.
For now, the company has shown that AI can help turn a high-level chip specification into working FPGA hardware in less than two weeks. The next question is whether the same process works when Redwood becomes a manufactured chip.
